Server processors: Opteron

Unlike Intel, which opted to create a 64-bit processor compatible with the x86 instruction set, AMD has opted for a simpler design, using as K7 platform (used in Athlon 32-bit). Adding new registrars, support the memory addresses of 64 bits, new instructions and a number of other changes, come to a processor capable of running both 32-bit instructions and 64-bit instructions natively, without loss of performance. This allowed the 64-bit processor fitted with the new instruction set was popularized, initially on servers (with the Opteron) and then in desktops with Athlon 64 and its successors. Over time, Intel itself was forced to give dishonest, developing the EM64, which is nothing more than an implementation of the instruction set's 64-bit AMD.

Early models of the Opteron was launched in 2003. They were single-core processors based on the SledgeHammer core, produced using a technique of 0.13 micron. They all use 1 MB of L2 cache, but are divided into three distinct series.

1xx series processors are the cheapest, but do not support multiprocessing, they were destined to workstations and small servers. The 2xx series processors support two processors, competing with contemporary models of the Xeon DP, while the 8xx series processors support the use of 4 or 8 processors, competing directly with the Xeon MP. Signs supporting 8 processors are rare and expensive (the most common are the plates for 2 or 4 processors), but the few available models have been most successful in the market for high performance servers, giving rise to many current models.

The 1xx series based on the Opteron SledgeHammer includes 140 (1.4 GHz, 1 MB), 142 (1.6 GHz, 1 MB), 144 (1.8 GHz, 1 MB), 146 (2.0 GHz, 1 MB), 148 (2.2 GHz, 1 MB) and 150 (2.4 GHz, 1 MB). The 2xx series includes the Opteron 240 (1.4 GHz, 1 MB), 242 (1.6 GHz, 1 MB), 244 (1.8 GHz, 1 MB), 246 (2.0 GHz, 1 MB), 248 (2.2 GHz, 1 MB) and 250 (2.4 GHz, 1 MB), while the Opteron 8xx series includes the 840 (1.4 GHz, 1 MB), 842 (1.6 GHz, 1 MB), 844 (1.8 GHz, 1 MB), 846 (2.0 GHz, 1 MB), 848 (2.2 GHz, 1 MB) and 850 (2.4 GHz, 1 MB). As you can see, the processors of the three series are virtually identical. In fact, the only difference between an Opteron 150, 250 and a 850 is a configuration of HyperTransport links, which allow support for multiprocessing.

All these boards use socket 940 processors with 800 MHz bus, and require the use of registered DDR memory. Just like the current AMD, Opteron includes an integrated memory controller. With this, the type of memory supported is set directly by the processor, not by the chipset. Another peculiarity is that boards with support for multiple processors, each processor has its own set of memory modules, which directly accesses, unlike with SMP systems, where all processors share the same bus with the memory via the FSB.

The communication between processors is done through HyperTransport links, which are used not only for all exchange of data, but also to allow a processor has access to the memory modules connected to each other.

In comes NUMA (Non-Uniform Memory Architecture), which allows both processors to work using a unified address table. Thanks to the NUMA, each processor sees all the installed memory and made access to memory areas controlled by other processors are made via the HyperTransport links that connect.

Although single-core processors with 1 MB L2 cache sound obsolete within the current design, based on these pioneers SledgeHammer compared themselves favorably to the NetBurst Xeons based on the platform and were responsible for the increased use of AMD processors in servers, a branch that until then was dominated by Intel.

The second generation is represented by Opteron processors with core Venus (1xx series), Troy (2xx series) and Athens (8xx series), manufactured using a technique of 0.09 micron. They are still single-core processors, which maintain the L2 cache 1 MB SledgeHammer and the use of DDR memory, but offer a lower power consumption and support higher clock frequencies.

These three series were followed by dual-core versions, launched in March 2005, based on the colors Denmark (models 165, 170, 175, 180 and 185), Italy (models 265, 270, 275, 280, 285 and 290) and Egypt (models 865, 870, 875, 880, 885 and 890), all with 2x 1 MB L2 cache and clocked at 1.8 GHz (x65 models) to 2.8 GHz (x90 models). They were soon on the market, for Socket 940 boards still used and registered DDR memory, a platform that at the time was already considered outdated.

The upgrade came on line in August 2006 with the launch of the processors based on the color Santa Ana and Santa Rosa (coincidentally the same code name that Intel has chosen for the fourth generation Centrino platform), which brought support for DDR2 . Since both are still manufactured using the technique of 0.09 micron, they are still dual-core processors, with only 2x 1 MB L2 cache, like their predecessors. Nevertheless, the use of DDR2 memory performance increased considerably.

These processors use Socket F boards which, like Intel's LGA 771 socket, the system uses LGA (Land Grid Array), where the contact pins are moved from the CPU to the socket, creating a bed of contacts, on which the processor is installed. Socket F has no less than 1207 contacts, needed to accommodate the three HyperTransport busses independent, used for communication between the processors:

At the time, Intel had already launched the Woodcrest Xeons based on the core, together with the Core 2 Duo (also widely used in servers due to relatively low cost and good performance), began to slowly recover the space won by AMD in previous years. AMD is seen then required to reduce the price of the chips and compete with Intel on the basis of cost.

The answer came in September 2007 with the launch of quad-core versions of Opteron-based core Barcelona chips produced using a technique of 0065 micron.

Unlike core Clovertown Xeons with and Harpertown (among others) that are composed of two dual-core processors that share the same tunnel, Barcelona is a native quad-core processor. This gives a certain advantage in terms of performance, because all communication between processors is done through an internal HyperTransport bus and not through the FSB.

The core Barcelona-based processors include 512 KB of L2 cache per core (2MB total) plus a 2 MB L3 cache shared between the four cores, totaling 4 MB of cache. The use of shared L3 cache reduces duplication of information in cases where the cores are working with the same set of information. Another advantage of the platform is that the memory controller is integrated directly into the processor (rather than a component of the chipset), which reduces the latency of memory access and reduces the need for a larger cache. The combination of these factors allow the Barcelona can be competitive, while offering only a third of the cache that the Harpertown.

In addition to the L3 cache and the use of four cores, Barcelona includes a number of other improvements over previous processors, as the inclusion of 128-bit SSE units (capable of processing instructions in one cycle), improvements in decoders instructions and on the bus with cache, expansion of the buffers of the memory controller, improvements in the operation of caches and branch prediction circuit, which resulted in a series of incremental gains.