PCI Express: compatibility, data lines and PCIe 2.0

A key feature of the PCI Express is that it is a bus-to-peer, where each device has a unique channel of communication with the chipset. In traditional PCI, the bus is shared by all devices connected to it, which can create bottlenecks, such as plates socket 7.

Some purists argue that the PCI Express bus is not in a strict sense, since the term "bus" came to describe a communication channel shared by several devices or peripherals. But I am of the opinion that this kind of preciousness should be avoided. Technical terms evolve and are adapted, as well as technology. In all the documentation is used the term "PCI Express bus," referring to the PCI Express (and also the USB, Firewire and others) as "bus", or "bus". The designation has been officially adopted.

PCI Express is also a serial bus and not a parallel bus such as PCI. Previously, the electronics were very slow, so the solution to create faster buses was to add more tracks and transmit multiple bits at a time. Examples of parallel buses are parallel ports, used by older printers, theIDE ports and also own the PCI bus.

With the advancement of technology, designers began to have difficulty in creating parallel buses faster, because the large number of tracks operating at high frequency electromagnetic noise and created problems of timing. The solution was going to invest in serial buses, where they are used only one or two pairs of tracks and drivers more sophisticated, capable of transmitting at higher frequencies.

With fewer tracks, the problem of noise and interference is eliminated and data can be transmitted in the frequency allowed by the circuit without problems of timing. Currently, just making more sense to use a very fast driver circuit, one bit at a time, than trying to create a complicated bus, which transmits 16 or 32 bits per cycle.

While manufacturers have struggled to keep the timing of the signals of the PCI-X is only 133 MHz transmitters of the PCI Express bus can operate at 2.5 GHz without any problems.

Examples of serial buses, are the USB, Serial ATA and PCI Express. The performance difference between the current buses in relation to older buses is brutal: a parallel port working in EPP mode only transmits 8 megabits per second, while a USB 2.0 reaches 480 megabits. A port IDE ATA-133 transmits 133 MB / s, while SATA 600 reaches 600 MB / s. PCI offers only 133 MB / s, shared by all devices as a PCI Express 2.0 x16 reaches incredible 8 GB / s.

Starting from the basics, there are 4 types of PCI Express slots, ranging from x1 to x16. The number indicates how many rows of data are used by the slot and thus the available bandwidth.

There are two versions in use PCI Express, PCI Express 1.x and PCI Express 2.0. PCI Express 1.x is the initial standard (completed in 2002), while the PCI Express 2.0 is the latest version (completed in January 2007), which transmits at twice the speed. Despite the difference, the two standards are intercompatíveis: except in rare cases of incompatibility, there are no problems installing a PCI Express 2.0 on a PCI Express 1.1, or vice versa, but in both cases the speed is limited by the slower .

Each line of PCI Express uses 4 data pins (two for two to send and receive), operating in full-duplex (ie they are able to transmit and receive data simultaneously). The PCI Express 1.x have 250 MB / s in each direction per line data, while the PCI Express 2.0 have 500 MB / s per line.

Due to this characteristic, it is common for manufacturers to disclose the PCI Express transmits 500 MB / s in standard 1.x and 1000 MB / s in the 2.0 standard, but these are unrealistic values, because only occur in situations where large amounts data needed to be transmitted simultaneously in both directions.

Along with the use of serial bus, another major innovation of the PCI Express was to allow combining multiple rows of data in a single slot, multiplying the available bandwidth. Thus, we have 250 MB / s bandwidth on PCIe 1.1 x1 slots, 1 GB / s x4 slots, 2 GB / s in x8 slots and 4 GB / s x16 slots. In the case of boards with PCIe 2.0, double speed, 500 MB / s for the x1 slots, 2 GB / s x4 slots, 4 GB / s in x8 slots and incredible 8 GB / s x16 slots.

The original standard also provided the use of x2 and x32 slots, but they were never implemented. In practice, the 8x slots are also very rare, so you will only see slots 1x, 4x and 16x the current cards.

In all formats, the slot is divided into two sections. The first contains the contacts of electrical power and is equal in all slots, while the second includes the contacts database, which increase in number according to the number of rows of data:

This organization was developed so that there is backward compatible with all form factors. As a result, the x16 slots are also compatible with cards x1, x4 and x8 and x4 slots are also compatible with x1 cards (and the hypothetical plate x2).

When connecting a x1 card in a x16 slot, for example, the additional contacts are useless. As you can imagine, the controller is smart enough to disable the data lines inactive. If you know what you're doing, you can even cover some of the contacts with tape to disable the data lines and thus measure the performance of the card if used in slots with only 8 or 4 lines (as done in some reviews) .

There are also cases of motherboard slots with x4 or x8 "open." They have the edge connector, allowing you to fit larger plates, leaving the extra contacts out:

This solution is used in cases where the manufacturer wants to offer the possibility of using two video cards in CrossFire or SLI, even if the chipset only offers 4 lines of data for the second slot. As you can imagine, the use of only 4 lines create a bottleneck that reduces the performance of the second plate, but at least the possibility exists.

There is also the possibility of creating slots "neutered", where we have one x16 slot with only 8 data lines, or one x4 slot, with only one line, for example. These slots behave exactly the same way that a slot x1 or one x4 slot open, changing only the physical fit. As these cases is just a different use of lines of data (and no electrical connections), the slots are still fully compatible with all kinds of cards, only the data channel becomes slower.

Thanks to all this flexibility, we have some interesting cases such as this Intel D975BX the picture below. It has three PCI Express 16x slots (one with 16 data lines and the other with only 8 lines), two legacy PCI slots and no PCIe x1 or x4 (you would use one of the x16 slots if needed to install an expansion card any) :

In conclusion, PCI Express uses a coding system called 8b/10b, which are included two additional bits for each byte of data transmitted. These additional bits lifted the need to use additional pins to send the sync signal, which greatly simplified the design and improved reliability, but on the other hand reduced the actual volume of data transmitted.

It is because of this feature to 2.5 gigabits (PCIe 1.x) or 5.0 gigabits (in PCIe 2.0) band that every row of data is equivalent to only 250 and 500 MB / s data rather than the 312.5 and 625, which be the result of the traditional division by 8.